SAA7724H Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7724H Car radio digital signal processor Preliminary specification 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor CONTENTS 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.6 6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 6.9 6.9.1 Features GENERAL INFORMATION DSP radio system SAA7724H Sample rates ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Voltage regulator Audio analog front-end Selector diagram Realization of the mon mode input with AIN Realization of the differential ADIFF input Realization of the auxiliary input with volume control Supplies and references AD decimation paths (DAD) LDF and AUX decimation path ADF and audio decimation path Digital audio input/output General External I2S-bus input/output ports External SPDIF input EPICS host I2S-bus port Sample rate converter IF_AD IF_AD single block diagram IF_AD detailed functional description AUDIO_EPICS specific information AUDIO_EPICS start-up AUDIO_EPICS memory overview SDAC output path DAC upsampling filter DAC noise shaper DAC Co DEM scrambler Multi-bit SDAC Analog summer function SDAC application diagram Reset block functional overview Asynchronous reset 6.10 6.10.1 6.10.2 6.10.3 6.10.4 6.11 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 7 8 9 10 10.1 11 11.1 11.1.1 11.2 11.3 11.4 11.5 12 12.1 12.2 12.3 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 Clock circuit and oscillator Circuit description External clock input mode Crystal oscillator supply Application guidelines PLL circuits RDS General description RDS I/O modes RDS demodulator RDS bit buffer RDS/RBDS decoder LIMITING VALUES THERMAL RESISTANCE DC CHARACTERISTICS AC CHARACTERISTICS Timing diagrams I2C-BUS CONTROL I2C-bus protocol Protocol of the I2C-bus mands MPI data transfer formats Reset initialization Defined I2C-bus address I2C-bus memory map...