NXP Semiconductors SAA7724H
The SAA7724H runs at a master clock of 43.2 MHz. The microcontroller interfaces to the RF/IF and SAA7724H via an I2C-bus. The IF co-processor and audio co-processor interfaces to the SAA7724H via an I2S-bus.FEATURES
GENERAL INFORMATION DSP radio system SAA7724H Sample rates ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONALDESCRIPTION
Voltage regulator Audio analog front-end Selector diagram Realization of the common mode input with AIN Realization of the differential ADIFF input Realization of the auxiliary input with volume control Supplies and references AD decimation paths (DAD) LDF and AUX decimation path ADF and audio decimation path Digital audio input/output General External I2S-bus input/output ports External SPDIF input EPICS host I2S-bus port Sample rate converter IF_AD IF_AD single block diagram IF_AD detailed functional description AUDIO_EPICS specific information AUDIO_EPICS start-up AUDIO_EPICS memory overview SDAC output path DAC upsampling filter DAC noise shaper DAC CoDEM scrambler Multi-bit SDAC Analog summer function SDAC application diagram Reset block functional overview Asynchronous reset 6.10 6.10.1 6.10.2 6.10.3 6.10.4 6.11 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.1...