Full PDF Text Transcription for SSTUA32864 (Reference)
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SSTUA32864. For precise diagrams, and layout, please refer to the original PDF.
www.DataSheet4U.com SSTUA32864 1.8 V configurable registered buffer for DDR2-667 RDIMM applications Rev. 01 — 12 May 2005 Product data sheet 1. General description The SST...
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ev. 01 — 12 May 2005 Product data sheet 1. General description The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration (when LOW) to B configurati
SSTUA32864 Datasheet
