SSTUH32864 Datasheet | NXP Semiconductors

description The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are patible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUH32864 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and un-driven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be pletely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when ing out of reset, the register will bee active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUH32864 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The device monitors...