SSTUH32866 Datasheet | NXP Semiconductors

description The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a patible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM. The SSTUH32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, pares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs bined with the parity input bit. The SSTUH32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm × 5.5 mm). The SSTUH32866 is identical to SSTU32866 in function and performance, with higher-drive outputs optimized to drive heavy load nets (for example, stacked DRAMs) while maintaining speed and signal integrity. 2. Features s Configurable register supporting DDR2 Registered DIMM applications s Higher output drive strength version of SSTU32866 optimized for high-capacitive load nets s Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode s Controlled output impedance drivers enable optimal signal integrity and speed s Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) s Supports up to 450 MHz clock frequency of operation s Optimized pinout for high-density DDR2 module design s Chip-selects minimize power consumption by gating data outputs from changing state s Supports SSTL_18 data inputs s Checks parity on the DIMM-independent data...