TDA10025HN - Dual cable demodulator

Product Overview

NXP

TDA10025HN Dual cable demodulator by NXP - Datasheet Preview — Datasheet preview – TDA10025HN

Datasheet Details

Part number	TDA10025HN
Manufacturer	NXP
File Size	106.85 KB
Description	Dual cable demodulator
Datasheet	TDA10025HN Datasheet
Additional preview pages of the TDA10025HN datasheet.

Product details

Description

The TDA10025HN is a Dual Cable Downstream Processor.

The Cable Downstream Processor (CDP) implements the physical interfaces and protocols required to provide the highest quality services of an in-band DOCSIS, EuroDOCSIS, DVB and OpenCable Set-Top Box (STB).

Features

QPSK, 16 QAM, 32 QAM, 64 QAM, 128 QAM and 256 QAM Demodulator.
ITU-T J83 Annex A, B and C FEC.
Transport Stream Multiplex Frame (TSMF) module for Annex C compliance.
Time interleaved parallel mode or serial mode for Transport Stream (TS) interface.
On chip PLL for crystal frequency multiplication (16 MHz external).
Reuse of the tuner clock, saving one crystal.
Embedded 12-bit ADC.
3.3 V and 1.2 V power supplies.
Low power < 235 mW for dual stream ope.

📁 Similar Datasheet

TDA10023HT - Single chip DVB-C/MCNS channel receiver (Philips)
TDA1002A - Recording and Playback Amplifier (ETC)
TDA1003A - Motor Regulator and Bias/Erase Oscillator Circuit (Philips)
TDA10046HT - Single-Chip DVB-T Channel Decoder (Philips)
TDA1006A - MOTOR REGULATOR WITH AUTOMATIC TAPE END INDICATOR (ETC)
TDA1010A - Audio Power Output (ETC)
TDA1013 - 4W audio power amplifier (ETC)
TDA1013A - Audio Power Output (ETC)

Other Datasheets by NXP

TDA10021HT - DVB-C channel receiver
TDA1001B - Interference and noise suppression circuit for FM receivers
TDA1001BT - Interference and noise suppression circuit for FM receivers
TDA10045H - DVB-T channel receiver
TDA1005A - FREQUENCY MULTIPLEX PLL STEREO DECODER
TDA1005AT - FREQUENCY MULTIPLEX PLL STEREO DECODER

Published: Jul 10, 2020 |