TDA8960 Description
TDA8960 I2C-bus interface I2C-bus interface to initialize and monitor the demodulator and Forward Error Correction (FEC) decoder. Operation without I2C-bus control is possible (default). See the ATSC URL on ‘http://.atsc.’ for the following related documents:.
TDA8960 Key Features
- One-chip Advanced Television Systems mittee (ATSC)-pliant demodulator and concatenated trellis (Viterbi)/Reed Solomon de
- 0.4 µm process
- 3.3 V device
- 64-lead QFP64 package
- Boundary scan test
- Output format: 8-bit wide bus. DOCUMENT REFERENCES 8-VSB demodulator
- On-chip digital circuitry for tuner Automatic Gain Control (AGC)
- Square root raised cosine filter with 11.5% roll-off factor
- Fully internal carrier recovery loop
- Mostly internal clock recovery and AGC loops with programmable loop filters