UJA1069TW Datasheet | NXP Semiconductors

UJA1069 LIN fail-safe system basis chip Rev. 04 - 28 October 2009 Product data sheet 1. General description The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete ponents which are mon in every Electronic Control Unit (ECU) with a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications which control various power and sensor peripherals by using LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices: - LIN transceiver pliant with LIN 2.0 and SAE J2602, and patible with LIN 1.3 - Advanced independent watchdog - Dedicated voltage regulator for microcontroller - Serial peripheral interface (full duplex) - Local wake-up input port - Inhibit/limp-home output port In addition to the advantages of integrating these mon ECU functions in a single package, the fail-safe SBC offers an intelligent bination of system-specific functions such as: - Advanced low-power concept - Safe and controlled system start-up behavior - Advanced fail-safe system behavior that prevents any conceivable deadlock - Detailed status reporting on system and sub-system levels The UJA1069 is designed to be used in bination with a microcontroller and a LIN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations the fail-safe SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation. The UJA1069 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. NXP Semiconductors UJA1069 LIN fail-safe system basis chip 2. Features 2.1 General I Contains a full set of LIN ECU functions: N LIN transceiver N Voltage regulator for the microcontroller (5.0 V) N Enhanced window watchdog with on-chip oscillator N Serial Peripheral Interface (SPI) for the microcontroller N ECU power management system N Fully...