XA-H3 Datasheet | NXP Semiconductors

DESCRIPTION The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking. By supporting of up to 32 MB of external memory, these devices provide a low-cost solution to embedded applications of any plexity. Features like DMA, memory controller and four advanced UARTs help solve I/O intensive tasks with a minimum of CPU load. The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The XA-H3/H4 devices are members of the Philips XA (e Xtended Architecture) family of high performance 16-bit microcontrollers. The XA-H3 and XA-H4 are designed to significantly minimize the need for external ponents. FEATURES - Large Memory Support (up to 6 MB external) - De-multiplexed Address/Data Bus - Six Programmable Chip Selects - Support for Unified Memory - allows easy user modification of all code - External ISP Flash support for easy code download - Dynamic Bus Timing - each of 6 chip selects has individual programmable bus timing. - 32 Programmable General Purpose I/O Pins - Four UARTs with 230.4 kbps capability - Eight DMA Channels - Dynamic Bus Sizing - each of 6 Chip Selects can be programmed for 8-bit or 16-bit bus. Table 1. XA-H3 and XA-H4 features parison Feature Maximum External Memory (Harvard Memory Mode) Maximum External Memory (Unified Memory Mode) Memory Controller supports both Harvard and Unified architectures De-multiplexed Address/Data Bus DRAM Controller DMA Channels Dynamic Bus Sizing Dynamic Bus Timing Programmable Chip Selects General Purpose IO Pins Potential Interrupt Pins Interrupts (programmable priority) XA-H3 6 MB 6 MB Yes Yes No 8 Yes Yes 6 33 16 7 Standard SW 4 High Priority SW 13 Hardware Event Counter/Timers Baud Rate Generators1 Serial Ports Maximum Serial Data Rates Match Characters Hardware Autobaud SCP/SPI Bus NOTE: 1. Can be used as additional counters if not needed as BRGs. 2 plus Watchdog 4 4 UARTS asynch to 230.4...