XA-H4 Datasheet | NXP Semiconductors

DESCRIPTION The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking. By supporting of up to 32 MB of external memory, these devices provide a low-cost solution to embedded applications of any plexity. Features like DMA, memory controller and four advanced USARTs help solve I/O intensive tasks with a minimum of CPU load. The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The XA-H3/H4 devices are members of the Philips XA (e Xtended Architecture) family of high performance 16-bit microcontrollers. The XA-H3 and XA-H4 are designed to significantly minimize the need for external ponents. FEATURES - Large Memory Support - De-multiplexed Address/Data Bus - Six Programmable Chip Selects - Support for Unified Memory - allows easy user modification of all code - External ISP Flash support for easy code download - Dynamic Bus Timing - each of 6 chip selects has individual programmable bus timing. - 32 Programmable General Purpose I/O Pins - Four USARTs with 230.4 kbps capability - Eight DMA Channels - Dynamic Bus Sizing - each of 6 Chip Selects can be programmed for 8-bit or 16-bit bus. ADDITIONAL XA-H4 FEATURES (NOT AVAILABLE ON XA-H3) - plete DRAM controller supports up to four banks of 8 MB each - Memory controller supports 16 MB in Unified Mode - Memory controller supports 32 MB in Harvard Mode - Serial ports are USARTs - Synchronous capability up to 1 Mbps, and include HDLC/SDLC support - Four Match Characters are supported on each USART in Async Mode - Hardware Autobaud on all four USARTs in Async Mode - USARTs are improved 85C30 style 1999 Sep 24 Philips Semiconductors Preliminary specification Single-chip 16-bit microcontroller Table 1. XA-H3 and XA-H4 features parison Feature Maximum External Memory (Harvard Memory Mode) Maximum External Memory (Unified Memory Mode) Memory Controller supports both Harvard and...