Datasheet4U Logo Datasheet4U.com

NT256D64S88A2GM - 256MB DDR SO-DIMM

General Description

NT256D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank high-speed memory array.

The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR SDRAMs in 400 mil TSOP packages.

Key Features

  • JEDEC Standard 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) DDR SDRAM.
  • Performance :.
  • 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8 w w a D . w S a t e e h U 4 t m o . c.
  • Data is read or written on both clock edges.
  • DRAM DLL aligns DQ and DQS transitions with clock transitions.
  • Address and control signals are fully synchronous to positive clock edge PC1600 - 8B 2 100 10 200 PC2100 - 75B 2.5 133 7.5 266 - 7K 2.

📥 Download Datasheet

Datasheet Details

Part number NT256D64S88A2GM
Manufacturer Nanya Technology
File Size 151.50 KB
Description 256MB DDR SO-DIMM
Datasheet download datasheet NT256D64S88A2GM Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
NT2520SB Crystal Oscillator NDK
NT2520SB CRYSTAL OSCILLATOR NDK
NT2012 WIREWOUND COMMON MODE FILTER TOKO
NT2012F WIREWOUND COMMON MODE FILTER TOKO
NT2903 Single Chip FM Transceiver ETC

Other Datasheets by Nanya Technology

Part Number Description
NT256D64S88A0G 256MB DIMM
NT256D64S88AAG 256MB DIMM
NT256D64S88ABG 256MB DIMM
NT256D64S88B0G 256MB DDR DIMM
NT256D64S88B1G 256MB DDR DIMM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM 200pin One Bank Unbuffered DDR SO-DIMM Based on DDR266/200 32Mx8 SDRAM Features • JEDEC Standard 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) DDR SDRAM. • Performance : • 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8 w w a D . w S a t e e h U 4 t m o .c • Data is read or written on both clock edges • DRAM DLL aligns DQ and DQS transitions with clock transitions. • Address and control signals are fully synchronous to positive clock edge PC1600 - 8B 2 100 10 200 PC2100 - 75B 2.5 133 7.5 266 - 7K 2 133 7.5 266 MHz ns MHz Unit • Programmable Operation: - DIMM CAS Latency: 2, 2.