NT5DS128M4BF Overview
They are all based on Nanya’s 110 nm design process. The address bits registered coincident with the Read or Write mand are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write The 512Mb DDR SDRAM is a high-speed CMOS, dynamic burst lengths of 2, 4, or 8 locations.
NT5DS128M4BF Key Features
- DDR 512M bit, die B, based on 110nm design rules
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes