NT5DS128M4BS
Overview
NT5DS128M4BF, NT5DS128M4BT, NT5DS64M8BF, NT5DS64M8BT, NT5DS32M16BF and NT5DS32M16BT are die B of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 110 nm design process. accessed.
- DDR 512M bit, die B, based on 110nm design rules
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2 / 2.5 (6K & 75B), 2.5 / 3 (5T) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.5V ± 0.2V (6K & 75B) VDD = VDDQ = 2.6V ± 0.1V (5T)
