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NT5DS32M16CG - 512Mb DDR SDRAM

General Description

Die C of 512Mb SDRAM devices based using DDR interface.

They are all based on Nanya’s 90 nm design process.

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

Key Features

  • DDR 512M bit, Die C, based on 90nm design rules.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is centeraligned with data for writes.
  • Differential clock inputs (CK and CK).
  • Four internal banks for concurrent operation.
  • Data mask (DM) for write data.

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Datasheet Details

Part number NT5DS32M16CG
Manufacturer Nanya Techology
File Size 2.15 MB
Description 512Mb DDR SDRAM
Datasheet download datasheet NT5DS32M16CG Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NT5DS32M16CG NT5DS64M8CG NT5DS128M4CG NT5DS32M16CS NT5DS64M8CS NT5DS128M4CS 512Mb DDR SDRAM Features • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2.