NT5CB256M8GN Datasheet | Nanya

Feature - VDD = VDDQ = 1.5V ± 0.075V(JEDEC Standard Power Supply) - VDD = VDDQ = 1.35V -0.0675V/+0.1V (Backward patible to VDD = VDDQ = 1.5V ±0.075V) - 8 Internal memory banks (BA0- BA2) - Differential clock input (CK, ) - Programmable Latency: 5, 6, 7, 8, 9, 10, 11 -  WRITE Latency (CWL): 5,6,7,8,9 - POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2 clock - Programmable Sequential / Interleave Burst Type Through ZQ pin (RZQ:240 ohm±1%) - Programmable Burst Length: 4, 8 - 8n-bit prefetch architecture - Output Driver Impedance Control - Differential bidirectional data strobe - Internal(self) calibration:Internal self calibration - OCD Calibration - Dynamic ODT (Rtt_Nom & Rtt_WR) - Auto Self-Refresh - Self-Refresh Temperature - Ro HS pliance and Halogen free - Packages: 78-Balls BGA for x4, x8 ponents REV 1.1 08/ 2011 2Gb DDR3 SDRAM G-Die NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN Description The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 2,147,483,648 bits. It is internally configured as an octal-bank DRAM. The 2Gb chip is organized as 64Mbit x 4 I/O x 8 bank and 32Mbit x 8 I/O x 8 banks . These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to ply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V and 1.35V -0.0675V/+0.1V power supply and are available in BGA packages. REV 1.1 08/ 2011 2Gb DDR3 SDRAM G-Die NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN Pin Configuration - 78 balls BGA Package (x4) < TOP View> See the balls...