NT5CC128M16IP
Key Features
- JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
- Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes
- Power Saving Mode - Partial Array Self Refresh (PASR) 1 - Power Down Mode
- Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)
- Signal Synchronization - Write Leveling via MR settings 6 - Read Leveling via MPR
- Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1353 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V) Options
- Speed Grade (CL-TRCD-TRP) 2 - 2133 Mbps / 14-14-14 - 1866 Mbps / 13-13-13 - 1600 Mbps / 11-11-11
