DS92LV3242 Overview
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The panion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, deskews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus. On-chip data...
DS92LV3242 Key Features
- Wide Operating Range Embedded Clock SER/DES
- Up to 32-bit parallel LVCMOS data
- 20 to 85 MHz parallel clock
- Up to 2.72 Gbps application data paylod
- Selectable Serial LVDS Bus Width
DS92LV3242 Applications
- Dual Lane Mode (20 to 50 MHz)
- Quad Lane Mode (40 to 85 MHz) Simplified Clocking Architecture
