DS92LV3242 Datasheet | Texas Instruments

FEATURES - 2 Wide Operating Range Embedded Clock SER/DES - Up to 32-bit Parallel LVCMOS Data - 20 to 85 MHz Parallel Clock - Up to 2.72 Gbps Application Data Paylod - Selectable Serial LVDS Bus Width - Dual Lane Mode (20 to 50 MHz) - Quad Lane Mode (40 to 85 MHz) - Simplified Clocking Architecture - No Separate Serial Clock Line - No reference Clock Required - Receiver Locks to Random Data - On-Chip Signal Conditioning for Robust Serial Connectivity - Transmit Pre-Emphasis - Data Randomization - DC-Balance Encoding - Receive Channel Deskew - Supports up to 10m CAT-5 at 2.7 Gbps - Integrated LVDS Terminations - Built-in AT-SPEED BIST for End-to-End System Testing - AC-Coupled Interconnect for Isolation and Fault Protection - > 4KV HBM ESD Protection - Space-Saving 64-pin TQFP Package - Full Industrial Temperature Range : -40° to +85°C APPLICATIONS - Industrial Imaging (Machine-Vision) and Control - Security & Surveillance Cameras and Infrastructure - Medical imaging - Up to 30 bits per Pixel, VGA to HD Video Transport and Display DESCRIPTION The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The panion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus. On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Preemphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to ining data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation. By embedding the clock in the data payload and including signal conditioning functions, the Channel Link II Ser Des devices reduce trace count, eliminate skew issues, simplify design effort and...