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100310 - Low Skew 2:8 Differential Clock Driver

General Description

The 100310 is a low skew a bit differential clock driver which is designed to select between two separate differen

tial clock inputs.

The low output to output skew « 50 ps) is maintained for either clock input.

A LOW on the select pin (SEL) selects CLKINA.

Key Features

  • Low output to output skew.
  • Differential inputs and outputs.
  • Allows multiplexing between two clock inputs.
  • Voltage compensated operating range: -4.2V to -5.7V Ordering Code: See Section 5 Logic Symbol CLKINA ClKINA CLKINB CLKINB SEL ClKg CLKg CLKj CLKj CLK2 CLK2 ClK3 CLK3 CLK. CLK. CLKs CLKs CLKs CLKs ClK7 CLK7 --t>--vss Tl/F/10943-1 Connection Diagram 28-Pln pcc rn ClKe ClKe ax7VCCAax7 NC ClKINB [TI [Q] [!] [l][IIIII Pin Names CLKINn.
  • ClKINn SEL.

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Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
100311 Low Skew 1:9 Differential Clock Driver
100315 Low-Skew Quad Clock Driver
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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.o... CW) .oo... ~National D Semiconductor 100310 Low Skew 2:8 Differential Clock Driver General Description The 100310 is a low skew a·bit differential clock driver which is designed to select between two separate differen· tial clock inputs. The low output to output skew « 50 ps) is maintained for either clock input. A LOW on the select pin (SEL) selects CLKINA. CLKINA and a HIGH on the SEl pin selects the CLKINS. ClKINS inputs. The 100310 is ideal for those applications that need the ability to freely select between two clocks. or to maintain the ability to switch to an alternate or backup clock should a problem arise with the primary clock source. A Vss output is provided for single-ended operation.