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54AC377 - Octal D Flip-Flop

Description

The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered.

Features

  • n ICC reduced by 50% Logic Symbols IEEE/IEC DS100290-1 DS100290-2 Pin Names D0.
  • D7 CE Q0.
  • Q7 CP.

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www.DataSheet4U.com 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable February 1999 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
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