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54ACT109 - Dual JK Positive Edge-Triggered Flip-Flop

Download the 54ACT109 datasheet PDF. This datasheet also covers the 54AC109 variant, as both devices belong to the same dual jk positive edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

Key Features

  • n n n n ICC reduced by 50% Outputs source/sink 24 mA ’ACT109 has TTL-compatible inputs Standard Military Drawing (SMD).
  • ’AC109: 5962-89551.
  • ’ACT109: 5962-88534 Logic Symbol IEEE/IEC DS100267-1 DS100267-7 Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 DS100267-2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (54AC109_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
54ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES Texas Instruments
54ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES Texas Instruments
54ACT11010 Triple 3-Input Positive-NAND Gates Texas Instruments
54ACT11011 TRIPLE 3-INPUT POSITIVE-AND GATES Texas Instruments
54ACT11021 DUAL 4-INPUT POSITIVE-AND GATES Texas Instruments

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop
54ACT138 1-of-8 Decoder/Demultiplexer
54ACT139 Dual 1-of-4 Decoder/Demultiplexer
54ACT151 8-Input Multiplexer
54ACT153 Dual 4-Input Multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop August 1998 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’AC/’ACT74 data sheet) by connecting the J and K inputs together.