Datasheet4U Logo Datasheet4U.com

54F299 - Octal Universal Shift/Storage Register

Description

The ’F299 is an 8-bit universal shift storage register with TRI-STATE outputs Four modes of operation are possible hold (store) shift left shift right and load data The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins Additional outputs Q0

Features

  • Y Common parallel I O for reduced pin count Y Additional serial inputs and outputs for expansion Y Four operating modes shift left shift right load and store Y TRI-STATE outputs for bus-oriented.

📥 Download Datasheet

📁 Similar Datasheet

  • 54F299 - 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS (Texas Instruments)
  • 54F20 - DUAL 4-INPUT POSITIVE-NAND GATES (Texas Instruments)
  • 54F241 - Octal Buffers/Line Drivers (Texas Instruments)
  • 54F242 - QUAD BUS TRANCEIVERS (Motorola)
  • 54F243 - QUAD BUS TRANCEIVERS (Motorola)
  • 54F243 - QUADRUPLE BUS TRANSCEIVERS (Texas Instruments)
  • 54F244 - Octal Buffers/Line Drivers (Texas Instruments)
  • 54F245 - Octal Bidirectional Transceiver (Texas Instruments)
  • 54F253 - Dual 1-of-4 Data Selector/Multiplexers (Texas Instruments)
  • 54F257 - Quadruple 2-Line To 1-Line Data Selectors/Multiplexers (Texas Instruments)
Other Datasheets by National Semiconductor
  • 54F20 - Dual 4-Input NAND Gate
  • 54F219 - 64-Bit Random Access Memory
  • 54F2244 - Octal Buffer/Line Driver
  • 54F240 - Octal Buffers/Line Drivers
  • 54F241 - Octal Buffers/Line Drivers
  • 54F243 - Quad Bus Transceiver with TRI-STATE Outputs
  • 54F244 - Octal Buffers/Line Drivers
  • 54F245 - Octal Bidirectional Transceiver

Full PDF Text Transcription

Click to expand full text
Obsolete 54F 74F299 Octal Universal Shift Storage Register with Common Parallel I O Pins May 1995 54F 74F299 Octal Universal Shift Storage Register with Common Parallel I O Pins General Description The ’F299 is an 8-bit universal shift storage register with TRI-STATE outputs Four modes of operation are possible hold (store) shift left shift right and load data The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins Additional outputs Q0 – Q7 are provided to allow easy serial cascading A separate active LOW Master Reset is used to reset the register Features Y Common parallel I O for reduced pin count Y Additional serial inputs and outputs for expansion Y Four operating modes shift left shift right load and store Y TRI-STATE outputs for
Published: |