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74LVX125 - Low-Voltage Quad Buffer

General Description

The LVX125 contains four independent non-inverting buffers with TRI-STATE outputs The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems

Key Features

  • Y Input voltage level translation from 5V to 3V Y Ideal for low power low noise 3 3V.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVX125 Low-Voltage Quad Buffer with TRI-STATE Outputs January 1996 74LVX125 Low-Voltage Quad Buffer with TRI-STATE Outputs General Description The LVX125 contains four independent non-inverting buffers with TRI-STATE outputs The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems Features Y Input voltage level translation from 5V to 3V Y Ideal for low power low noise 3 3V applications Y Available in SOIC JEDEC SOIC EIAJ and TSSOP packages Y Guaranteed simultaneous switching noise level and dy- namic threshold performance Logic Symbol Connection Diagram IEEE IEC Pin Assignment for SOIC and TSSOP TL F 12007 – 1 Truth Table Pin Names An Bn On Description Inputs Outputs Inputs An Bn LL LH HX H e HIGH Voltage Level L e LOW Voltage Level Z e High I