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CGS54CT2526 - 1-to-8 Minimum Skew Clock Driver

This page provides the datasheet information for the CGS54CT2526, a member of the CGS74CT2526 1-to-8 Minimum Skew Clock Driver family.

Datasheet Summary

Description

On the multiplexed clock device the SEL pin is used to determine which CLKn input will have an active effect on the outputs of the circuit When SEL e 1 the CLK1 input is selected and when SEL e 0 the CLK0 input is selected The non-selected CLKn input will not have any effect on the logical output le

Features

  • Y These CGS devices implement National’s FACTTM family Y Ideal for signal generation and clock distribution Y Guaranteed pin to pin and part to part skew Y Multiplexed clock input (’2526) Y Guaranteed 2 kV minimum ESD protection Y Symmetric output current drive of 24 mA for IOL IOH Y ’CT has TTL-compatible inputs Y These products are identical to 74AC ACT2525 and 2526 Y Available as Mil Aero versions 54AC ACT2525 54AC ACT2526 Logic Symbols ’2525 Connection Diagrams Pin Assignment for DIP and S.

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Datasheet preview – CGS54CT2526

Datasheet Details

Part number CGS54CT2526
Manufacturer National Semiconductor
File Size 170.20 KB
Description 1-to-8 Minimum Skew Clock Driver
Datasheet download datasheet CGS54CT2526 Datasheet
Additional preview pages of the CGS54CT2526 datasheet.

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Other Datasheets by National Semiconductor
  • CGS54CT2525 - 1-to-8 Minimum Skew Clock Driver
  • CGS54C2525 - 1-to-8 Minimum Skew Clock Driver
  • CGS54C2526 - 1-to-8 Minimum Skew Clock Driver
  • CGS100P2530 - PECl-TTl1 to 10 Minimum Skew Clock Driver
  • CGS100P2531 - PECl-TTl 2 to 10 Minimum Skew Clock Driver
  • CGS2534TV - Quad 1 to 4 Clock Drivers
  • CGS2534V - Quad 1 to 4 Clock Drivers
  • CGS2535TV - Commercial Quad 1 to 4 Clock Drivers/Industrial Quad 1 to 4 Clock Drivers

Full PDF Text Transcription

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CGS74C2525  CGS74CT2525  CGS74C2526  CGS74CT2526 1-to-8 Minimum Skew Clock Driver September 1995 CGS74C2525  CGS74CT2525 CGS74C2526  CGS74CT2526 1-to-8 Minimum Skew Clock Driver The CGS ’C CT2525 is a minimum skew clock driver with one input driving eight outputs specifically designed for signal generation and clock distribution applications The ’2525 is designed to distribute a single clock to eight separate receivers with low skew across all outputs during both the tPLH and tPHL transitions The ’2526 is similar to the ’2525 but contains a multiplexed clock input to allow for systems with dual clock speeds or systems where a separate test clock has been implemented Features Y These CGS devices implement National’s FACTTM family Y Ideal for signal generation and clock distribution
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