CGS74LCT2524 Datasheet | National Semiconductor

Description This minimum skew clock driver is a 3V option of the current CGS74CT2524 Minimum Skew Clock Driver and is designed for Clock Generation and Support (CGS) applications operating at low voltage, high frequencies. This device guarantees minimum output skew across the outputs of a given device. Skew parameters are also provided as a means to measure duty cycle requirements as those found in high speed clocking systems. This minimum skew clock driver with one input driving four outputs, is specifically designed for signal generation and clock distribution applications. Features - Ideal for low power/low noise high speed applications - Guaranteed: - 300 ps pin-to-pin skew (t OSHL and t OSLH) - Implemented on National's FACT™ family process - 1 input to 4 outputs low skew clock distribution - Symmetric output current drive: 12 m A IOH/IOL - Industrial temperature of - 40°C to +85°C - 8-pin SOIC package - Low dynamic power consumption above 20 MHz - Guaranteed 2 k V ESD protection Logic Symbol Connection Diagrams Pin Assignment SOIC (MO) The output pins act as a single entity and will follow the state of the CLK when the clock distribution chip is selected. Pin Description Pin Names CLK O0- O3 Description Clock Input Outputs Truth Table Inputs CLK L = Low Logic Level H = High Logic Level Outputs O0- O3 See NS Package Number M08A FACT™ is a trademark of Fairchild Semiconductor © 2011 National Semiconductor Corporation 11956 11956 Version 5 Revision 3 Print Date/Time: 2011/09/21 13:18:34 .national. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Voltage Diode Current (IIK) V = - 0.5V V = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current...