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CLC031A - SMPTE 292M/259M Digital Video Deserializer / Descrambler

Datasheet Summary

Description

The CLC031A SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate c

Features

  • a variabledepth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. The unique multi-functional I/O port of the CLC031A provides external access to functions and data stored in the configuration and control registers. This feature all.

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Datasheet Details

Part number CLC031A
Manufacturer National Semiconductor
File Size 401.39 KB
Description SMPTE 292M/259M Digital Video Deserializer / Descrambler
Datasheet download datasheet CLC031A Datasheet
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www.DataSheet4U.com CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs September 2004 CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs General Description The CLC031A SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data.
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