Datasheet4U Logo Datasheet4U.com

DM54174 - Hex/Quad D Flip-Flops

General Description

These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) version

Key Features

  • complementary outputs from each flip-flop Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output Features Y 174 contains six flip-flops with single-rail outputs Y 175 c.

📥 Download Datasheet

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DM5417 Hex Buffers with High Voltage Open-Collector Outputs
DM54173 Quad D Registers
DM54175 Hex/Quad D Flip-Flops
DM5410 Triple 3-Input NAND Gates
DM54121 One-Shot with Clear and Complementary Outputs
DM54122 Retriggerable Resettable Multivibrator
DM54123 Dual Retriggerable One-Shot with Clear and Complementary Outputs
DM54125 Quad TRI-STATE Buffers
DM54132 DM54132/DM74132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs
DM5414 Hex Inverter with Schmitt Trigger Inputs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear June 1989 54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear General Description These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) version features complementary outputs from each flip-flop Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output Features Y 174 cont