Datasheet4U Logo Datasheet4U.com

DM54L95 - 4-Bit Parallel Access Shift Registers

Description

These 4-bit registers feature parallel and serial inputs parallel output mode control and two clock inputs The registers have three modes of operation Parallel (broadside) load Shift right (the direction QA toward QD) Shift left (the direction QD toward QA) Parallel loading is accomplished by applyi

Features

  • Y Y Typical maximum clock frequency 14 MHz Typical power dissipation mW Connection Diagram Dual-In-Line Package Order Number DM54L95J or DM54L95W See NS Package Number J14A or W14B TL F 6638.
  • 1 Function Table Inputs Mode Control H H H L L L Clocks 2 (L) H 1 (R) X X X H X X X X H L X X X X X Serial A X a QB X X X X X X X X Parallel B X b QC X X X X X X X X C X c QD X X X X X X X X D X d d X X X X X X X X QAO a QBn QAO H L QAO QAO QAO QAO QAO QBO b QCn QBO QAn QAn QBn QBO QBO QBO QBO.

📥 Download Datasheet

Datasheet preview – DM54L95

Datasheet Details

Part number DM54L95
Manufacturer National Semiconductor
File Size 105.12 KB
Description 4-Bit Parallel Access Shift Registers
Datasheet download datasheet DM54L95 Datasheet
Additional preview pages of the DM54L95 datasheet.

📁 Similar Datasheet

  • DM54L89A - 64-BIT READ/WRITE MEMORIES (ETC)
  • DM54LS47 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS48 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS49 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54141 - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM54155 - Dual 2-Line to 4-Line Decoders/Demultiplexers (ETC)
  • DM5441A - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM5446A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5447A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5448 - BCD/7-Segment Decoder/Driver (MSI)
Other Datasheets by National Semiconductor
  • DM54L93 - Decade/ Divide-by-12/ and Binary Counters
  • DM54L00 - Quad 2-Input NAND Gates
  • DM54L00 - Quad 2-Input NAND Gates
  • DM54L02 - Quad 2-Input NOR Gates
  • DM54L04 - Hex Inverting Gate
  • DM54L10 - Triple 3-Input NAND Gates
  • DM54L73 - Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
  • DM54L74 - Dual Positive Edge Triggered D Flip-Flop

Full PDF Text Transcription

Click to expand full text
DM54L95 4-Bit Parallel Access Shift Registers June 1989 DM54L95 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel and serial inputs parallel output mode control and two clock inputs The registers have three modes of operation Parallel (broadside) load Shift right (the direction QA toward QD) Shift left (the direction QD toward QA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input During loading the entry of serial data is inhibited Shift right is accomplished on the high-to-low transition of clock 1 when the mode control is low shift left is accomplished on
Published: |