Datasheet4U Logo Datasheet4U.com

DM54LS502 - 8-Bit Successive Approximation Register

Description

The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and al

Features

  • Y Y Y Low power Schottky version of 2502 Storage and control for successive approximation A to D conversion Performs serial-to-parallel conversion Connection Diagram Dual-In-Line Package Logic Symbol TL F 10189.
  • 2 VCC e Pin 16 GND e Pin 8 TL F 10189.
  • 1 Order Number DM54LS502J DM54LS502W DM74LS502WM or DM74LS502N See NS Package Number J16A M16B N16E or W16A Pin Names D S CP QD CC Q0.
  • Q7 Q7.

📥 Download Datasheet

Datasheet preview – DM54LS502

Datasheet Details

Part number DM54LS502
Manufacturer National Semiconductor
File Size 133.13 KB
Description 8-Bit Successive Approximation Register
Datasheet download datasheet DM54LS502 Datasheet
Additional preview pages of the DM54LS502 datasheet.

📁 Similar Datasheet

  • DM54LS47 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS48 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS49 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54L89A - 64-BIT READ/WRITE MEMORIES (ETC)
  • DM54141 - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM54155 - Dual 2-Line to 4-Line Decoders/Demultiplexers (ETC)
  • DM5441A - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM5446A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5447A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5448 - BCD/7-Segment Decoder/Driver (MSI)
Other Datasheets by National Semiconductor
  • DM54LS503 - 8-Bit Successive Approximation Register
  • DM54LS00 - Quad 2-Input NAND Gates
  • DM54LS02 - Quad 2-Input NOR Gates
  • DM54LS03 - Quad 2-Input NAND Gates with Open-Collector Outputs
  • DM54LS04 - Hex Inverting Gates
  • DM54LS08 - Quad 2-Input AND Gates
  • DM54LS10 - Triple 3-Input NAND Gates
  • DM54LS109A - Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs

Full PDF Text Transcription

Click to expand full text
DM54LS502 DM74LS502 8-Bit Successive Approximation Register April 1992 DM54LS502 DM74LS502 8-Bit Successive Approximation Register General Description The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and all other outputs HIGH Subsequent clocks shift this Q7 LOW signal downstream which simultaneously backfills the register such that the first serial data (D input) bit is stored in Q7 the second bit in Q6 the third in Q5 etc The serial input data is also synchronized by an auxiliary flip-flop and brought out on QD Designed primarily for use in the
Published: |