Datasheet Details
| Part number | DM54LS502 |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 133.13 KB |
| Description | 8-Bit Successive Approximation Register |
| Download | DM54LS502 Download (PDF) |
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Overview: DM54LS502 DM74LS502 8-Bit Successive Approximation Register April 1992 DM54LS502 DM74LS502 8-Bit Successive Approximation.
| Part number | DM54LS502 |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 133.13 KB |
| Description | 8-Bit Successive Approximation Register |
| Download | DM54LS502 Download (PDF) |
|
|
|
The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and all other outputs HIGH Subsequent clocks shift this Q7 LOW signal downstream which simultaneously backfills the register such that the first serial data (D input) bit is stored in Q7 the second bit in Q6 the third in Q5 etc The serial input data is also synchronized by an auxiliary flip-flop and brought out on QD Designed primarily for use in the successive approximation technique for analog-to-digital conversion the LS502 can also be used as a serial-to-parallel converter ring counter and as the storage and control element in recursive digital routines
| Part Number | Description |
|---|---|
| DM54LS503 | 8-Bit Successive Approximation Register |
| DM54LS00 | Quad 2-Input NAND Gates |
| DM54LS02 | Quad 2-Input NOR Gates |
| DM54LS03 | Quad 2-Input NAND Gates with Open-Collector Outputs |
| DM54LS04 | Hex Inverting Gates |
| DM54LS08 | Quad 2-Input AND Gates |
| DM54LS10 | Triple 3-Input NAND Gates |
| DM54LS109A | Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs |
| DM54LS11 | Triple 3-Input AND Gates |
| DM54LS112A | NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS |