DM54LS502 Datasheet | National Semiconductor

DM54LS502 DM74LS502 8-Bit Successive Approximation Register April 1992 DM54LS502 DM74LS502 8-Bit Successive Approximation Register General Description The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion plete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and all other outputs HIGH Subsequent clocks shift this Q7 LOW signal downstream which simultaneously backfills the register such that the first serial data (D input) bit is stored in Q7 the second bit in Q6 the third in Q5 etc The serial input data...