Datasheet Details
| Part number | DM54LS503 |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 126.36 KB |
| Description | 8-Bit Successive Approximation Register |
| Download | DM54LS503 Download (PDF) |
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Overview: DM54LS503 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control) April 1992 DM54LS503 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control).
| Part number | DM54LS503 |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 126.36 KB |
| Description | 8-Bit Successive Approximation Register |
| Download | DM54LS503 Download (PDF) |
|
|
|
The ’LS503 register is basically the same as the ’LS502 except that it has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths A HIGH signal on E after a START operation forces Q7 HIGH and prevents the device from accepting serial data With the E input of an ’LS503 connected to the CC output of a preceding (more significant) device the ’LS503 will be inhibited until the preceding device is filled causing its CC output to go LOW This LOW signal then enables the ’LS503 to accept the serial data on subsequent clocks For a description of the starting shifting and conversion operations please see the ’LS502 data sheet
| Part Number | Description |
|---|---|
| DM54LS502 | 8-Bit Successive Approximation Register |
| DM54LS00 | Quad 2-Input NAND Gates |
| DM54LS02 | Quad 2-Input NOR Gates |
| DM54LS03 | Quad 2-Input NAND Gates with Open-Collector Outputs |
| DM54LS04 | Hex Inverting Gates |
| DM54LS08 | Quad 2-Input AND Gates |
| DM54LS10 | Triple 3-Input NAND Gates |
| DM54LS109A | Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs |
| DM54LS11 | Triple 3-Input AND Gates |
| DM54LS112A | NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS |