Datasheet4U Logo Datasheet4U.com

DM74ALS138 - 3 to 8 Line Decoder/Demultiplexer

General Description

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times In high-performance memory systems these decoders can be used to minimize the effects of system decoding When used with high-speed mem

Key Features

  • fully buffered inputs presenting only one normalized load to its driving circuit All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design Features Y Designed specifically for high speed Memory decoders Data transmission systems Y 3- to 8-line decoder incorporates 3 enable inputs to simplify cascading and or data reception Y Low power dissipation 23 mW typ Y Switching specifications guaranteed over full tempera- ture and VCC range Y Advanced.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DM74ALS138 3 to 8 Line Decoder/Demultiplexer Fairchild Semiconductor
DM74ALS133 13-Input NAND Gate Fairchild Semiconductor
DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches Fairchild Semiconductor
DM74ALS1000A Quadruple 2-Input NAND Buffer Fairchild Semiconductor
DM74ALS1004 Hex Inverting Driver Fairchild Semiconductor

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DM74ALS132 DM74ALS132 Quad 2-Input NAND Gate with Schmitt Trigger Inputs
DM74ALS1242 Quad Bidirectional Bus Drivers
DM74ALS14 Hex Inverter with Schmitt Trigger Inputs
DM74ALS151 1 of 8 Line Data Selector/Multiplexer
DM74ALS390 Dual 4-Bit Decade Counters

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74ALS138 3 to 8 Line Decoder Demultiplexer August 1995 DM74ALS138 3 to 8 Line Decoder Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times In high-performance memory systems these decoders can be used to minimize the effects of system decoding When used with high-speed memories the delay times of these decoders are usually less than the typical access time of the memory This means that the effective system delay introduced by the decoder is negligible The ALS138 decodes one-of-eight lines based upon the conditions at the three binary select inputs and the three enable inputs Two active-low and one active-high enable inputs reduce the need f