Datasheet Details
| Part number | DM74LS109A |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 135.00 KB |
| Description | Dual Positive-Edge-Triggered J-K Flip-Flops |
| Datasheet | DM74LS109A_NationalSemiconductor.pdf |
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Overview: 54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and plementary Outputs June 1989 54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear.
| Part number | DM74LS109A |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 135.00 KB |
| Description | Dual Positive-Edge-Triggered J-K Flip-Flops |
| Datasheet | DM74LS109A_NationalSemiconductor.pdf |
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This device contains two independent positive-edge-triggered J-K flip-flops with plementary outputs The J and K data is accepted by the flip-flop on the rising edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
DM74LS109A | Dual Positive-Edge-Triggered J-K Flip-Flop | Fairchild Semiconductor |
| Part Number | Description |
|---|---|
| DM74LS10 | Triple 3-Input NAND Gates |
| DM74LS107A | Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops |
| DM74LS11 | Triple 3-Input AND Gates |
| DM74LS112A | NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS |
| DM74LS125A | Quad TRI-STATE Buffers |
| DM74LS132 | NAND Gates |
| DM74LS138 | Decoders/Demultiplexers |
| DM74LS139 | Decoders/Demultiplexers |
| DM74LS14 | HEX Inverters |
| DM74LS151 | Data Selector/Multiplexer |