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DM74LS197 - Presettable Binary Counters

General Description

The ’LS197 ripple counter contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter State changes are initiated by the falling edge of the clock The ’LS197 has a Master Reset (MR) input which overrides all other inputs and asynchronously forces all

Key Features

  • Y Y Y High counting rates Typically 70 MHz Asynchronous preset Asynchronous master reset Connection Diagram Dual-In-Line Package TL F 10180.
  • 1 Order Number DM74LS197M or DM74LS197N See NS Package Number M14A or N14A Mode Select Table Pin Names CP0 CP1 MR P0.
  • P3 PL Q0 Q1.
  • Q3.

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More Datasheets from National Semiconductor (now Texas Instruments)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74LS197 Presettable Binary Counters February 1992 DM74LS197 Presettable Binary Counters General Description The ’LS197 ripple counter contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter State changes are initiated by the falling edge of the clock The ’LS197 has a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flipflops This preset feature makes the circuit usable as a programmable counter The circuit can also be used as a 4-bit latch loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH For detail specificati