DP83864 Description
Features The DP83864 is an extremely efficient full featured Quad IEEE pliant 10BASE-T,100BASE-TX, 1000BASE-T Physical Layer transceiver with integrated PMD sublayers Adaptive equalization and Baseline Wander p. to support 10BASE-T, 100BASE-TX and 1000BASE-T IEEE 802.3u Auto-Negotiation and Parallel Detection Ethernet protocols. Fully auto-negotiates between 1000 Mb/s, 100 Mb/s, The DP83864 contains four integrated...
DP83864 Key Features
- IEEE pliant 10BASE-T,100BASE-TX, 1000BASE-T Physical Layer transceiver with integrated PMD sublayers
- Adaptive equalization and Baseline Wander p. to support 10BASE-T, 100BASE-TX and 1000BASE-T
- IEEE 802.3u Auto-Negotiation and Parallel Detection Ethernet protocols
- Fully auto-negotiates between 1000 Mb/s, 100 Mb/s, The DP83864 contains four integrated ultra low power and 10 Mb/s full
- 2.5 V/3.3 V MAC interfaces: CMOS technology, fabricated at National’s South Portland, Maine facilities
- IEEE 802.3u MII with programmable bus ordering
- IEEE 802.3z GMII with programmable bus ordering The DP83864 is designed for easy implementation of 10/100/1000 Mb/s Ethe
- Reduced GMII (RGMII) ver. 1.3 directly to Twisted Pair media via an external transformer
- Serial GMII (SGMII) This device interfaces directly to the MAC layer through the
- LED support (Link10, Link100, Link1000, Activity and IEEE 802.3u Standard Media Independent Interface (MII) Duplex indic
DP83864 Applications
- One management port per chip
- Switches with 10/100/1000 Mb/s capable ports
- Supports Auto-MDIX/polarity at all speeds
- High speed uplink ports with redundancies (backbone)
- One JTAG interface per chip
- Servers with Quad Ethernet ports