Datasheet4U Logo Datasheet4U.com

DP8403 - Error Detection and Correction Circuits

This page provides the datasheet information for the DP8403, a member of the DP8402A Error Detection and Correction Circuits family.

Description

The DP8402A DP8403 DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is s

Features

  • Y Detects and corrects single-bit errors Y Detects and flags double-bit errors Y Built-in diagnostic capability Y Fast write and read cycle processing times Y Byte-write capability DP8402A and DP8403 Y Fully pin and function compatible with TI’s SN74ALS632A thru SN74ALS635 series System Environment TL F 8535.
  • 1 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 8535 RRD-B30M105 Printed in U S A Simplified Functional Bloc.

📥 Download Datasheet

Datasheet preview – DP8403

Datasheet Details

Part number DP8403
Manufacturer National Semiconductor
File Size 495.69 KB
Description Error Detection and Correction Circuits
Datasheet download datasheet DP8403 Datasheet
Additional preview pages of the DP8403 datasheet.
Other Datasheets by National Semiconductor

Full PDF Text Transcription

Click to expand full text
DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s) Obsolete PRELIMINARY August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s) General Description The DP8402A DP8403 DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is stored along with the data word during the memory write cycle During the memory read cycle the 39-bit words from memory are processed by the EDACs to determine if errors have occurred in memory Single-bit errors in the 32-bit data word are flagged and corr
Published: |