This page provides the datasheet information for the DP8420V, a member of the DP84T22 microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers family.
Description
The DP8420V 21V 22V-33 DP84T22-25 dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420V 21V 22V-33 DP84T22-25 generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to auto
Features
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On chip high precision delay line to guarantee critical DRAM access timing parameters microCMOS process for low power High capacitance drivers for RAS CAS WE and DRAM address on chip On chip support for nibble page and static column DRAMs TRI-STATE outputs (DP84T22 only) Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Selection of controller speeds 25 MHz and 33 MHz On board Port A Port B (DP8422V DP84T22 only) refresh.
DP8420V 21V 22V-33 DP84T22-25 microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers
May 1992
DP8420V 21V 22V-33 DP84T22-25 microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers
General Description
The DP8420V 21V 22V-33 DP84T22-25 dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420V 21V 22V-33 DP84T22-25 generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back ac
DP8420V Datasheet
