DP8421A Datasheet | National Semiconductor

Description The DP8420A 21A 22A dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420A 21A 22A generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional feature of the DP8422A is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip of Pins (PLCC) 68 68 84 of Address Outputs 9 10 11 Features On chip high precision delay line to guarantee critical DRAM access timing parameters micro CMOS process for low power High capacitance drivers for RAS CAS WE and DRAM address on chip On chip support for nibble page and static column DRAMs Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Selection of controller speeds 20 MHz and 25 MHz On board Port A Port B (DP8422A only) refresh arbitration logic Direct interface to all major microprocessors (application notes available) 4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable) Direct Drive Memory Capacity 4 Mbytes 16 Mbytes 64 Mbytes Access Ports Available Single Access Port Single Access Port Dual Access Ports (A and B) Control DP8420A DP8421A DP8422A Largest DRAM Possible 256 kbit 1 Mbit 4 Mbit Block Diagram DP8420A 21A 22A DRAM Controller TL F 8588 - 5 FIGURE 1 TRI-STATE is a registered trademark of National Semiconductor Corporation Staggered Refresh TM is a...