This page provides the datasheet information for the DP8430V, a member of the DP8432V (DP8430V - DP8432V) microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers family.
Description
The DP8430V 31V 32V dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8430V 31V 32V generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM a
Features
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On chip high precision delay line to guarantee critical DRAM access timing parameters microCMOS process for low power High capacitance drivers for RAS CAS WE and DRAM address on chip On chip support for nibble page and static column DRAMs Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Can use a single clock source Up to 33 MHz operating frequency On board Port A Port B (DP8432V only) refresh arbitration logic Direct inte.
DP8430V 31V 32V-33 microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers
July 1993
DP8430V 31V 32V-33 microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers
General Description
The DP8430V 31V 32V dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8430V 31V 32V generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wa
DP8430V Datasheet
