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DS8837 - Hex Unified Bus Receiver

General Description

The DS7837 DS8837 are high speed receivers designed for use in bus organized data transmission systems interconnected by terminated 120X impedance lines The external termination is intended to be 180X resistor from the bus to the a 5V logic supply together with a 390X resistor from the bus to ground

Key Features

  • Y Y Y Y Y Y Y Y Low receiver input current for normal VCC or VCC e 0V (15 mA typ) Six separate receivers per package Built-in receiver input hysteresis (1V typ) High receiver noise immunity (2V typ) Temperature insensitive receiver input thresholds track bus logic levels TTL compatible disable and output Molded or cavity dual-in-line or flat package High speed Typical.

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More Datasheets from National Semiconductor (now Texas Instruments)

Part Number Description
DS8830 Dual Differential Line Driver
DS8831 Dual TRI-STATE Line Driver
DS8832 Dual TRI-STATE Line Driver
DS8833 Quad TRI-STATE Bus Transceivers
DS8834 Quad TRI-STATE Bus Transceivers
DS8835 Quad TRI-STATE Bus Transceivers
DS8838 Quad Unified Bus Transceiver
DS8800 Dual Voltage Level Translator
DS8810 (DS8810 - DS8812) Quad 2-Input TTL MOS Interface Gate
DS8811 (DS8810 - DS8812) Quad 2-Input TTL MOS Interface Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS7837 DS8837 Hex Unified Bus Receiver February 1996 DS7837 DS8837 Hex Unified Bus Receiver General Description The DS7837 DS8837 are high speed receivers designed for use in bus organized data transmission systems interconnected by terminated 120X impedance lines The external termination is intended to be 180X resistor from the bus to the a 5V logic supply together with a 390X resistor from the bus to ground The receiver design employs a built-in input hysteresis providing substantial noise immunity Low input current allows up to 27 driver receiver pairs to utilize a common bus Disable inputs provide time discrimination Disable inputs and receiver outputs are TTL compatible Performance is optimized for systems with bus rise and fall times s 1 0 ms V Features Y Y Y Y Y Y Y Y Low recei