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DS90C032B - LVDS Quad CMOS Differential Line Receiver

General Description

TheDS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

Key Features

  • n >155.5 Mbps (77.7 MHz) switching rates n Accepts small swing (350 mV) differential signal levels n High Impedance LVDS inputs with power down n Ultra low power dissipation n 600 ps maximum differential skew (5V, 25˚C) n 6.0 ns maximum propagation delay n Industrial operating temperature range n Available in surface mount packaging (SOIC) n Pin compatible with DS26C32A, MB570 (PECL) and 41LF (PECL) n Supports OPEN and terminated input failsafe n Conforms to ANSI/TIA/EIA-644 LVDS standard Conne.

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📁 Similar Datasheet

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90C032BLVDS Quad CMOS Differential Line Receiver September 2003 DS90C032B LVDS Quad CMOS Differential Line Receiver General Description TheDS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. TheDS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE® function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing.