Datasheet4U Logo Datasheet4U.com

DS90C365 - +3.3V Programmable LVDS Transmitter

Download the DS90C365 datasheet PDF. This datasheet also covers the DS90C365MTD variant, as both devices belong to the same +3.3v programmable lvds transmitter family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS90C385 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Key Features

  • n 20 to 85 MHz shift clock support n Best.
  • in.
  • Class Set & Hold Times on TxINPUTs n Tx power consumption < 130 mW (typ) @85MHz Grayscale n Tx Power-down mode < 200µW (max) n Supports VGA, SVGA, XGA and Single/Dual Pixel SXGA. n Narrow bus reduces cable size and cost n Up to 2.38 Gbps throughput n Up to 297.5 Megabytes/sec bandwidth n 345 mV (typ) swing LVDS devices for low EMI n PLL requires no external components n Compatible with TIA/EIA-644 LVDS standard n Low profile 56-lead or.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90C365MTD_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90C385/DS90C365 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD)Link-85 MHz January 1999 DS90C385/DS90C365 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz General Description The DS90C385 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.