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DS90CF383 - +3.3V LVDS Transmitter

General Description

The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Key Features

  • n n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode ( < 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 227 Megabytes/sec bandwidth Up to 1.8 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Tran.

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📁 Similar Datasheet

Part Number Description Manufacturer
DS90CF383B +3.3V Programmable LVDS Transmitter Texas Instruments
DS90CF384A +3.3V LVDS Receiver Texas Instruments
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DS90CF386 3.3-V LVDS Receiver Texas Instruments
DS90CF388 Dual Pixel LVDS Display Interface Texas Instruments

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DS90CF384 +3.3V Programmable LVDS Transmitter
DS90CF384A +3.3V LVDS Receiver
DS90CF386 +3.3V LVDS Receiver
DS90CF388 Dual Pixel LVDS Display Interface
DS90CF388A Dual Pixel LVDS Display Interface/FPD-Link

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link— 65 MHz January 2000 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link— 65 MHz General Description The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec.