Datasheet4U Logo Datasheet4U.com

DS90CF383B - +3.3V Programmable LVDS Transmitter

General Description

The DS90CF383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Key Features

  • 1.
  • 23 No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or.
  • 5% Down Spread.
  • "Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low when Input Clock is Missing and When /PD Pin is Logic High.
  • 18 to 68 MHz Shift Clock Support.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DS90CF383 +3.3V LVDS Transmitter National Semiconductor
DS90CF384 +3.3V Programmable LVDS Transmitter National Semiconductor
DS90CF384A +3.3V LVDS Receiver National Semiconductor
DS90CF386 +3.3V LVDS Receiver National Semiconductor
DS90CF388 Dual Pixel LVDS Display Interface National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
DS90CF384A +3.3V LVDS Receiver
DS90CF384AQ +3.3V LVDS Receiver
DS90CF386 3.3-V LVDS Receiver
DS90CF388 Dual Pixel LVDS Display Interface
DS90CF363B +3.3V Programmable LVDS Transmitter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90CF383B www.ti.com SNLS178E – JULY 2004 – REVISED APRIL 2013 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz Check for Samples: DS90CF383B FEATURES 1 •23 No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread. • "Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low when Input Clock is Missing and When /PD Pin is Logic High.