DS90CF383B Overview
The DS90CF383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
DS90CF383B Key Features
- 23 No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied E
- Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or -5% Down Sprea
- "Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low when Input Clock is Missing and When /PD Pin is Lo
- 18 to 68 MHz Shift Clock Support
- Best-in-Class Set & Hold Times on TxINPUTs
- Tx Power Consumption < 130 mW (typ)
- 40% Less Power Dissipation Than BiCMOS
- Tx Power-down Mode < 60μW (typ)
- Supports VGA, SVGA, XGA and Dual Pixel
- Narrow Cus Reduces Cable Size and Cost
