DS90CF583 Datasheet PDF - National Semiconductor LVDS 24-Bit Color Flat Panel Display Link Specs

DS90CF583 - LVDS 24-Bit Color Flat Panel Display Link

Datasheet Summary

Description

The DS90CF583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Features

n n n n n n n n n n n n n 20 to 65 MHz shift clk support Up to 227 Mbytes/s bandwidth Cable size is reduced to save cost 290 mV swing LVDS devices for low EMI Low power CMOS design ( < 550 mW typ) Power-down mode saves power ( < 0.25 mW) PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Single pixel per clock XGA (1024 x 768) Supports VGA, SVGA, XGA and higher 1.8 Gbps throughput Block Diagrams DS012616-24.

Datasheet Details

Part number	DS90CF583
Manufacturer	National Semiconductor
File Size	274.74 KB
Description	LVDS 24-Bit Color Flat Panel Display Link
Datasheet	DS90CF583 Datasheet
Additional preview pages of the DS90CF583 datasheet.

📁 Similar Datasheet

DS90CF563 - LVDS (Texas Instruments)

DS90CF564 - LVDS (Texas Instruments)

DS90CF363B - +3.3V Programmable LVDS Transmitter (Texas Instruments)

DS90CF364 - +3.3V Programmable LVDS Transmitter (Texas Instruments)

DS90CF364A - +3.3V LVDS Receiver (Texas Instruments)

DS90CF366 - 3.3-V LVDS Receiver (Texas Instruments)

DS90CF383B - +3.3V Programmable LVDS Transmitter (Texas Instruments)

DS90CF384A - +3.3V LVDS Receiver (Texas Instruments)

DS90CF384AQ - +3.3V LVDS Receiver (Texas Instruments)

DS90CF386 - 3.3-V LVDS Receiver (Texas Instruments)

Full PDF Text Transcription

Click to expand full text

DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz November 1996 DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz General Description The DS90CF583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF584 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL) are transmitted at a rate of 455 Mbps per LVDS data channel.

Published: Mar 30, 2005 |