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DS90CR281 - 28-Bit Channel Link

General Description

The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Key Features

  • n n n n n n n n Narrow bus reduces cable size and cost ± 1V common mode range (ground shifting) 290 mV swing LVDS data transmission 1.12 Gbit/s data throughput Low swing differential current mode drivers reduce EMI Rising edge data strobe Power down mode Offered in low profile 56-lead TSSOP package Block Diagrams DS90CR281 DS90CR282 DS012638-27 DS012638-1 Order Number DS90CR281MTD See NS Package Number MTD56 Order Number DS90CR282MTD See NS Package Number MTD56 TRI-STATE ® is a registered.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90CR281/DS90CR282 28-Bit Channel Link July 1997 DS90CR281/DS90CR282 28-Bit Channel Link General Description The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR282 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 28 bits of TTL data are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 1.12 Gbit/s (140 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction.