DS90CR485 Overview
The DS90CR485 serializes the 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phaselocked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost.
