DS90LV001 Datasheet | National Semiconductor

Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the LLP (Leadless Leadframe Package) package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance. A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator. An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE. The DS90LV001 is offered in two package options, an 8 pin LLP and SOIC. Features n n n n n n n Single +3.3 V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold < ± 100 m V Fast propagation delay of 1.4 ns (typ) Low jitter 800 Mbps fully differential data path 100 ps (typ) of pk-pk jitter with PRBS = 223- 1 data pattern at 800 Mbps n patible with ANSI/TIA/EIA-644-A LVDS standard n 8 pin SOIC and space saving (70%) LLP package n Industrial Temperature Range Connection Diagram Top View DS101338-5 Order Number DS90LV001TM, DS90LV001TLD See NS Package Number M08A, LDA08A Block Diagram DS101338-2 © 2001 National Semiconductor Corporation DS101338 .national. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) LVCMOS/LVTTL...