GENERAL DESCRIPTION
In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like. This will allow the device to also fill the role of an LVPECL-LVDS translator. An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE. The DS90LV001 is offered in two package options, an 8 pin LLP and SOIC. FEATURES
n n n n n n n Single +3.3 V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold < ± 100 mV Fast propagation delay of 1.4 ns (typ) Low jitter 800 Mbps fully differential data path 100 ps (typ) of pk-pk jitter with PRBS = 223...
National Semiconductor
