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DS90LV001 - 3.3V LVDS-LVDS Buffer

General Description

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal.

Key Features

  • n n n n n n n Single +3.3 V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold < ± 100 mV Fast propagation delay of 1.4 ns (typ) Low jitter 800 Mbps fully differential data path 100 ps (typ) of pk-pk jitter with PRBS = 223.
  • 1 data pattern at 800 Mbps n Compatible with ANSI/TIA/EIA-644-A LVDS standard n 8 pin SOIC and space saving (70%) LLP package n Industrial Temperature Range Connection Diagram Top View DS101338-5 Order Number DS90LV001TM, DS.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90LV001 3.3V LVDS-LVDS Buffer April 2001 DS90LV001 3.3V LVDS-LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.