DS90LV001 Overview
The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to...
DS90LV001 Key Features
- 2 Single +3.3 V Supply
- LVDS Receiver Inputs Accept LVPECL Signals
- TRI-STATE Outputs
- Receiver Input Threshold < ±100 mV
- Fast Propagation Delay of 1.4 ns (Typ)
- Low Jitter 800 Mbps Fully Differential Data
- 100 ps (Typ) of pk-pk Jitter with PRBS = 223-1
- patible with ANSI/TIA/EIA-644-A LVDS
- 8 pin SOIC and Space Saving (70%) WSON
- Industrial Temperature Range
