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DS90LV012A - 3V LVDS Single CMOS Differential Line Receiver

General Description

The DS90LV012A and DS90LT012A are single CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates.

Key Features

  • n n n n n n n n n n n n n n n n n n Compatible with ANSI TIA/EIA-644-A Standard > 400 Mbps (200 MHz) switching rates 100 ps differential skew (typical) 3.5 ns maximum propagation delay Integrated line termination resistor (102Ω typical) Single 3.3V power supply design (2.7V to 3.6V range) Power down high impedance on LVDS inputs Accepts small swing (350 mV typical) differential signal levels LVDS receiver inputs accept LVDS/BLVDS/LVPECL inputs Supports open, short and terminated input fail-safe.

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DS90LV012A/DS90LT012A 3V LVDS Single CMOS Differential Line Receiver August 2002 DS90LV012A/DS90LT012A 3V LVDS Single CMOS Differential Line Receiver General Description The DS90LV012A and DS90LT012A are single CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology The DS90LV012A and DS90LT012A accept low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receivers also support open, shorted, and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions.