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DS90UR241 - DC-Balanced 24-Bit LVDS Serializer/Deserializer

This page provides the datasheet information for the DS90UR241, a member of the DS90UR124 DC-Balanced 24-Bit LVDS Serializer/Deserializer family.

Datasheet Summary

Description

The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Features

  • pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK. n Supports AC-coupling data transmission n Individual power-down controls for both Transmitter and Receiver n 1.8V VCM at LVDS input side n Embedded clock CDR (clock and data recovery) on Receiv.

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Datasheet Details

Part number DS90UR241
Manufacturer National Semiconductor
File Size 0.96 MB
Description DC-Balanced 24-Bit LVDS Serializer/Deserializer
Datasheet download datasheet DS90UR241 Datasheet
Additional preview pages of the DS90UR241 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer PRELIMINARY September 2006 DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90UR241/124 incorporates LVDS signaling on the high-speed I/O.
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