DS90UR241Q Datasheet | National Semiconductor

DS90UR241Q/DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset .. DS90UR241Q DS90UR124Q September 4, 2009 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18bit color depth - RGB666 + HS, VS, DE + 3 additional general purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90UR241/124 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range EMI is further reduced. In addition, the device Features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK. - 24:1 interface pression - Embedded clock with DC Balancing supports AC-coupled data transmission - Capable to drive up to 10 meters shielded twisted-pair - - - - - - - - - - cable No reference clock required (deserializer) Meets ISO 10605 ESD - Greater than 8 k V HBM ESD structure Hot plug support EMI Reduction - Serializer accepts spread spectrum input; data randomization and shuffling on serial link; Deserializer provides Adjustable PTO (progressive turnon) LVCMOS...